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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>RCWCAS, RCWCASA, RCWCASL, RCWCASAL -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">RCWCAS, RCWCASA, RCWCASL, RCWCASAL</h2>
      <p class="aml">Read Check Write Compare and Swap doubleword in memory reads a 64-bit doubleword from memory, and compares it against the value held in a register. If the comparison is equal, the value in a second register is conditionally written to memory. Storing back to memory is conditional on RCW Checks. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. This instruction updates the condition flags based on the result of the update of memory.</p>
      <ul>
        <li><span class="asm-code">RCWCASA</span> and <span class="asm-code">RCWCASAL</span> load from memory with acquire semantics.</li>
        <li><span class="asm-code">RCWCASL</span> and <span class="asm-code">RCWCASAL</span> store to memory with release semantics.</li>
        <li><span class="asm-code">RCWCAS</span> has neither acquire nor release semantics.</li>
      </ul>
    
    <h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_THE)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">A</td><td class="lr">R</td><td class="lr">1</td><td colspan="5" class="lr">Rs</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>1</td><td class="r">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td/><td class="droppedname">S</td><td colspan="6"/><td/><td/><td/><td colspan="5"/><td colspan="6"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">RCWCAS<span class="bitdiff"> (A == 0 &amp;&amp; R == 0)</span></h4><a id="RCWCAS_C64_rcwcomswap"/><p class="asm-code">RCWCAS  <a href="#sa_xs" title="64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_xt" title="64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>]</p></div><div class="encoding"><h4 class="encoding">RCWCASA<span class="bitdiff"> (A == 1 &amp;&amp; R == 0)</span></h4><a id="RCWCASA_C64_rcwcomswap"/><p class="asm-code">RCWCASA  <a href="#sa_xs" title="64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_xt" title="64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>]</p></div><div class="encoding"><h4 class="encoding">RCWCASAL<span class="bitdiff"> (A == 1 &amp;&amp; R == 1)</span></h4><a id="RCWCASAL_C64_rcwcomswap"/><p class="asm-code">RCWCASAL  <a href="#sa_xs" title="64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_xt" title="64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>]</p></div><div class="encoding"><h4 class="encoding">RCWCASL<span class="bitdiff"> (A == 0 &amp;&amp; R == 1)</span></h4><a id="RCWCASL_C64_rcwcomswap"/><p class="asm-code">RCWCASL  <a href="#sa_xs" title="64-bit general-purpose register to be compared and loaded (field &quot;Rs&quot;)">&lt;Xs&gt;</a>, <a href="#sa_xt" title="64-bit general-purpose register to be conditionally stored (field &quot;Rt&quot;)">&lt;Xt&gt;</a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveTHExt.0" title="function: boolean HaveTHExt()">HaveTHExt</a>() then UNDEFINED;
integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rs);

boolean acquire = A == '1';
boolean release = R == '1';
boolean tagchecked = n != 31;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xs&gt;</td><td><a id="sa_xs"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xt&gt;</td><td><a id="sa_xt"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode">if <a href="shared_pseudocode.html#impl-aarch64.IsD128Enabled.1" title="function: boolean IsD128Enabled(bits(2) el)">IsD128Enabled</a>(PSTATE.EL) then UNDEFINED;
bits(64) address;
bits(64) newdata = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t, 64];
bits(64) compdata = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[s, 64];
bits(64) readdata;
bits(4) nzcv;

<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescRCW.5" title="function: AccessDescriptor CreateAccDescRCW(MemAtomicOp modop, boolean soft, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescRCW</a>(<a href="shared_pseudocode.html#MemAtomicOp_CAS" title="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>, FALSE, acquire, release, tagchecked);

if n == 31 then
    <a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

(nzcv, readdata) = <a href="shared_pseudocode.html#impl-aarch64.MemAtomicRCW.4" title="function: (bits(4), bits(size)) MemAtomicRCW(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomicRCW</a>(address, compdata, newdata, accdesc);

PSTATE.&lt;N,Z,C,V&gt; = nzcv;
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, 64] = readdata;    // Return the old value when s!=31</p>
    </div>
  <h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</p>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
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